library verilog;
use verilog.vl_types.all;
entity dbg_sync_clk1_clk2 is
    generic(
        Tp              : integer := 1
    );
    port(
        clk1            : in     vl_logic;
        clk2            : in     vl_logic;
        reset1          : in     vl_logic;
        reset2          : in     vl_logic;
        set2            : in     vl_logic;
        sync_out        : out    vl_logic
    );
end dbg_sync_clk1_clk2;
